Position:
Analog Layout Intern ( at least 4-days each week)
Job Description:
Perform full-custom layout, physical verification and parasitic extraction for Freescale analog blocks.
Generate physical views for chip level integration.
Job Requirements:
1. Graduate students majoring in Electrical Engineering
2. Be familiar with layout-related EDA tools, such as Virtuoso/Virtuoso XL, Assura from Cadence and Calibre DRC/LVS from Mentor Graphic
3. Knowledge on CMOS fabrication process and device structure is a plus
4. Knowledge on analog circuit design is a plus
5. Good communication skill in English
有意者可投遞簡歷至[email protected]
聯(lián)系人： 金杰 （Amy King ）
聯(lián)系電話 ： 18013196767
